[ Pobierz całość w formacie PDF ]
definitions that do not change in normal data handling. This
Xon or Xoff character is pushed onto the RxFIFO for examination by
section is listed in the Register Map, Control .
the host CPU. The MR0(7) function operates regardless of the value
in MR0(3:2)
2. That part concerned with the transmission and reception of the
bit streams.
Xon/Xoff Interrupts
The Xon/Xoff logic generates interrupts only in response to
This part concerns the data status, FIFO fill levels, data error
recognizing either of the characters in the XonCR or XoffCR (Xon or
conditions, channel status, data flow control (hand shaking). This
Xoff Character Registers). The transmitter activity initiated by the
section is listed in the Register Map, Data .
Xon/Xoff logic or any CR command does not generate an interrupt.
1998 Sep 21 15
Philips Semiconductors Preliminary specification
Quad UART for 3.3V and 5V supply voltage SC28L194
Table 2. GCCR - Global Configuration Control Register
THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION. This register
has two addresses: x 0F and x 8F. The Global Configuration Control Register (GCCR) sets the type of bus cycle, interrupt vector modification
and the power-up or -down mode.
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
Bit 7 Bit 6 Bit 5:3 Bit 2:1 Bit 0
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved Sync bus cycles Reserved IVC, Interrupt Vector Control Power Down Mode
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ 00 - no interrupt vector ÁÁÁÁÁÁÁÁ
0 - async cycles ÁÁÁÁÁ 0 - Device enabled
1 - Sync, non-pipe-lined 01 - IVR 1 - Power down
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
Must be set to 0 Set to 0
cycle 10 - IVR + channel code
11 - IVR + interrupt type + channel code
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
GCCR(7): This bit is reserved for future versions of this device. If transmission/reception activities cease, and all processing for input
not set to zero most internal addressing will be disabled! change detection, BRG counter/timers and Address/Xon./Xoff
recognition is disabled.
GCCR(6): Bus cycle selection
Controls the operation of the host interface logic. If reset, the power Note: For maximum power savings it is recommended that all
on/reset default, the host interface can accommodate arbitrarily long switching inputs be stopped and all input voltage levels be within 0.5
bus I/O cycles. If the bit is set, the Quad UART expects four Sclk volt of the Vcc and Vss power supply levels.
cycle bus I/O operations similar to those produced by an i80386
To switch from the asynchronous to the synchronous bus cycle
processor in non-pipelined mode. The major differences in these
mode, a single write operation to the GCCR, terminated by a
modes are observed in the DACKN pin function. In Sync mode, no
negation of the CEN pin, is required. This cycle may be 4 cycles
negation of CEN is required between cycles.
long if the setup time of the CEN edge to Sclk can be guaranteed.
GCCR(2:1): Interrupt vector configuration The host CPU must ensure that a minimum of two Sclk cycles
The IVC field controls if and how the assertion of IACKN (the elapse before the initiation of the next (synchronous) bus cycle(s).
interrupt acknowledge pin) will form the interrupt vector for the Quad
A hardware or software reset is recommended for the unlikely
UART. If b 00, no vector will be presented during an IACKN cycle.
requirement of returning to the asynchronous bus cycling mode.
The bus will be driven high (xFF). If the field contains a b 01, the
contents of the IVR, Interrupt Vector Register, will be presented as
MR - Mode Registers
the interrupt vector without modification. If IVC = b 10, the channel
The user must exercise caution when changing the mode of running
code will replace the 3 LSBs of the IVR; if IVC = b 11 then a modified
receivers, transmitters or BRG counter/timers. The selected mode
interrupt type and channel code replace the 5 LSBs of the IVR.
will be activated immediately upon selection, even if this occurs
during the reception or transmission of a character. It is also
Note: The modified type field IVR(4:3) is:
possible to disrupt internal controllers by changing modes at critical
10 Receiver w/o error
times, thus rendering later transmission or reception faulty or
11 Receiver with error
impossible. An exception to this policy is switching from auto-echo
01 Transmitter
or remote loop back modes to normal mode. If the deselection
00 All remaining sources
occurs just after the receiver has sampled the stop bit (in most
GCCR(0): Power down control
cases indicated by the assertion of the channel s RxRDY bit) and
Controls the power down function. During power down the internal
the transmitter is enabled, the transmitter will remain in auto-echo
oscillator is disabled, interrupt arbitration and all data
mode until the end of the transmission of the stop bit.
1998 Sep 21 16
Philips Semiconductors Preliminary specification
Quad UART for 3.3V and 5V supply voltage SC28L194
Table 3. MR0- Mode Register 0
See XISR for more descriptions of MR0 Xon/Xoff functions
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
Bit 7 Bit 6 Bit 5:4 Bit 3:2 Bit 1:0
Xon/Xoff * transparencyÁÁÁÁÁÁÁÁ In-band flow control mode Address Recognition
Address Recognition * TxINT
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
transparency control
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
1 - flow control characters 1 - Address characters TxFIFO interrupt 00 - host mode, only the host CPU 00 - none
received are pushed onto received are pushed to level control may initiate flow control actions 01 - Auto wake
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
the RxFIFO RxFIFO 00 - empty through the CR 10 - Auto doze
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
01 - 3/4 empty 01 - Auto Transmitter flow control 11 - Auto wake and auto
0 - flow control characters 0 - Address characters
10 - 1/2 empty 10 - Auto Receiver flow control doze
received are not pushed received are not pushed
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
11 - not full 11 - Auto Rx and Tx flow control
onto the RxFIFO onto the RxFIFO
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
* If these bits are not 0 the characters will be stripped regardless of bits (3:2) or (1:0)
MR0[7 & 6] - Control the handling of recognized Xon/Xoff or RxFIFO to a level of 8 or less causes the Transmitter to emit an Xon [ Pobierz całość w formacie PDF ]
zanotowane.pl doc.pisz.pl pdf.pisz.pl ocenkijessi.opx.pl
definitions that do not change in normal data handling. This
Xon or Xoff character is pushed onto the RxFIFO for examination by
section is listed in the Register Map, Control .
the host CPU. The MR0(7) function operates regardless of the value
in MR0(3:2)
2. That part concerned with the transmission and reception of the
bit streams.
Xon/Xoff Interrupts
The Xon/Xoff logic generates interrupts only in response to
This part concerns the data status, FIFO fill levels, data error
recognizing either of the characters in the XonCR or XoffCR (Xon or
conditions, channel status, data flow control (hand shaking). This
Xoff Character Registers). The transmitter activity initiated by the
section is listed in the Register Map, Data .
Xon/Xoff logic or any CR command does not generate an interrupt.
1998 Sep 21 15
Philips Semiconductors Preliminary specification
Quad UART for 3.3V and 5V supply voltage SC28L194
Table 2. GCCR - Global Configuration Control Register
THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION. This register
has two addresses: x 0F and x 8F. The Global Configuration Control Register (GCCR) sets the type of bus cycle, interrupt vector modification
and the power-up or -down mode.
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
Bit 7 Bit 6 Bit 5:3 Bit 2:1 Bit 0
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved Sync bus cycles Reserved IVC, Interrupt Vector Control Power Down Mode
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ Reserved ÁÁÁÁÁÁÁÁÁÁÁÁ
Reserved ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ 00 - no interrupt vector ÁÁÁÁÁÁÁÁ
0 - async cycles ÁÁÁÁÁ 0 - Device enabled
1 - Sync, non-pipe-lined 01 - IVR 1 - Power down
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
Must be set to 0 Set to 0
cycle 10 - IVR + channel code
11 - IVR + interrupt type + channel code
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ
GCCR(7): This bit is reserved for future versions of this device. If transmission/reception activities cease, and all processing for input
not set to zero most internal addressing will be disabled! change detection, BRG counter/timers and Address/Xon./Xoff
recognition is disabled.
GCCR(6): Bus cycle selection
Controls the operation of the host interface logic. If reset, the power Note: For maximum power savings it is recommended that all
on/reset default, the host interface can accommodate arbitrarily long switching inputs be stopped and all input voltage levels be within 0.5
bus I/O cycles. If the bit is set, the Quad UART expects four Sclk volt of the Vcc and Vss power supply levels.
cycle bus I/O operations similar to those produced by an i80386
To switch from the asynchronous to the synchronous bus cycle
processor in non-pipelined mode. The major differences in these
mode, a single write operation to the GCCR, terminated by a
modes are observed in the DACKN pin function. In Sync mode, no
negation of the CEN pin, is required. This cycle may be 4 cycles
negation of CEN is required between cycles.
long if the setup time of the CEN edge to Sclk can be guaranteed.
GCCR(2:1): Interrupt vector configuration The host CPU must ensure that a minimum of two Sclk cycles
The IVC field controls if and how the assertion of IACKN (the elapse before the initiation of the next (synchronous) bus cycle(s).
interrupt acknowledge pin) will form the interrupt vector for the Quad
A hardware or software reset is recommended for the unlikely
UART. If b 00, no vector will be presented during an IACKN cycle.
requirement of returning to the asynchronous bus cycling mode.
The bus will be driven high (xFF). If the field contains a b 01, the
contents of the IVR, Interrupt Vector Register, will be presented as
MR - Mode Registers
the interrupt vector without modification. If IVC = b 10, the channel
The user must exercise caution when changing the mode of running
code will replace the 3 LSBs of the IVR; if IVC = b 11 then a modified
receivers, transmitters or BRG counter/timers. The selected mode
interrupt type and channel code replace the 5 LSBs of the IVR.
will be activated immediately upon selection, even if this occurs
during the reception or transmission of a character. It is also
Note: The modified type field IVR(4:3) is:
possible to disrupt internal controllers by changing modes at critical
10 Receiver w/o error
times, thus rendering later transmission or reception faulty or
11 Receiver with error
impossible. An exception to this policy is switching from auto-echo
01 Transmitter
or remote loop back modes to normal mode. If the deselection
00 All remaining sources
occurs just after the receiver has sampled the stop bit (in most
GCCR(0): Power down control
cases indicated by the assertion of the channel s RxRDY bit) and
Controls the power down function. During power down the internal
the transmitter is enabled, the transmitter will remain in auto-echo
oscillator is disabled, interrupt arbitration and all data
mode until the end of the transmission of the stop bit.
1998 Sep 21 16
Philips Semiconductors Preliminary specification
Quad UART for 3.3V and 5V supply voltage SC28L194
Table 3. MR0- Mode Register 0
See XISR for more descriptions of MR0 Xon/Xoff functions
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
Bit 7 Bit 6 Bit 5:4 Bit 3:2 Bit 1:0
Xon/Xoff * transparencyÁÁÁÁÁÁÁÁ In-band flow control mode Address Recognition
Address Recognition * TxINT
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
transparency control
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
1 - flow control characters 1 - Address characters TxFIFO interrupt 00 - host mode, only the host CPU 00 - none
received are pushed onto received are pushed to level control may initiate flow control actions 01 - Auto wake
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
the RxFIFO RxFIFO 00 - empty through the CR 10 - Auto doze
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
01 - 3/4 empty 01 - Auto Transmitter flow control 11 - Auto wake and auto
0 - flow control characters 0 - Address characters
10 - 1/2 empty 10 - Auto Receiver flow control doze
received are not pushed received are not pushed
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
11 - not full 11 - Auto Rx and Tx flow control
onto the RxFIFO onto the RxFIFO
ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ
* If these bits are not 0 the characters will be stripped regardless of bits (3:2) or (1:0)
MR0[7 & 6] - Control the handling of recognized Xon/Xoff or RxFIFO to a level of 8 or less causes the Transmitter to emit an Xon [ Pobierz całość w formacie PDF ]